A pervasive trend in modern integrated circuit manufacture is to downscale memory devices so as to increase the amount of data stored per unit area on an integrated circuit memory device, such as a flash memory device. Memory devices often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual-cell memory device, such as a charge trapping dielectric flash memory device, is capable of storing two bits (of data in a double-bit arrangement. That is, one bit can be stored using a first charge storing region on a first side of the memory device and a second bit can be stored using a second charge storing region on a second side of the memory device.
As shown in FIG. 1 and FIG. 2, a memory array can include a plurality of memory devices 10 organized in rows and columns, where a plurality of bitlines BL are oriented substantially parallel to one another along a first direction, and a plurality of wordlines WL are oriented substantially parallel to one another along a second direction that is perpendicular to the first direction. In such a configuration, a memory device 10 includes a pair of buried bitlines BL disposed within a semiconductor substrate 14. A charge trapping dielectric stack 16, which typically includes a non-conductive charge trapping layer 18 disposed between a bottom dielectric layer 20 and a top dielectric layer 22, is disposed over the semiconductor substrate 14. The charge trapping layer 18 typically includes a pair of charged storing regions on opposite sides of the layer between the buried bitlines BL. Over the top dielectric layer 22 is a wordline WL (also referred to as a gate electrode). In such a virtual ground architecture, the buried bitlines function as a source and a drain with an active channel region defined therebetween. Each memory device can be programmed, read, and erased by applying appropriate voltages to the source, drain, and wordline.
Where possible, it is desirable to downscale such memory devices, while still maintaining desirable qualities such as adequate data retention, and optimizing performance. However, memory device downscaling can result in a number of performance degrading effects. For example, at given width-pitch, as the width of the memory device is downscaled, the erase speed (e.g. the band-to-band (BTB) hot hole erase speed) can slow down considerably.
As shown in FIG. 2, one reason for this slow down is that BTB hot holes 30 generated in the vicinity of the bitline-to-substrate junction are capable of diffusing an appreciable distance away from the location of generation, both in the vertical direction and in the lateral direction (i.e., in the direction perpendicular to the cell channel). The probability of hole injection into the charge trapping layer is a function of the angle (A) and the magnitude of the hole velocity. If such BTB hot holes diffuse far enough so that they are no longer under the cell gate (wordline), they will have a very low probability of being injected into the charge trapping layer 18 under the gate (wordline), and, therefore, will not contribute to erasing the memory cell.
In view of the foregoing, there is a need for improved memory devices, such as charge trapping dielectric flash memory devices, which optimize scale and performance.